Conventionally, a CR delay circuit as shown in FIG. 9 has been used in an input interface part of a digital system so as to eliminate spike noise generated in an input signal. In such a conventional CR delay circuit 50, a signal input from an input terminal 51 is delayed by a resistance 53 and a capacitance 54 via an inverter element 52, and passes through a Schmitt trigger circuit 55 to be output to an output terminal 56. However, this circuit has some problems in that integration is difficult due to the use of the resistance (R) and the capacitance (C) and that a delay amount is set with insufficient accuracy.
In order to solve these problems, a spike noise eliminating circuit as a digital circuit has been proposed that eliminates both spike noise in a positive direction generated when an input signal is “0 (Lo)” and spike noise in a negative direction generated when an input signal is “1 (Hi)” (Patent Document 1).
As shown in FIG. 10, such a spike noise eliminating circuit 60 includes two delay gates 62 and 63, three AND gates 64, 65, and 66, and one OR gate 67. An input signal a input from an input terminal 61 is delayed by the delay gate 62 by a pulse width ΔT of the spike noise to be eliminated, resulting in a delay signal b. The delay signal b further is delayed by the other delay gate 63 by ΔT, resulting in a delay signal c.
The AND gate 64 receives the input signal a and the delay signal b, and supplies an output signal d to one input terminal of the OR gate 67. The AND gate 65 receives the input signal a and the delay signal c, and supplies an output signal e to a second input terminal of the OR gate 67. The AND gate 66 receives the delay signal b and the delay signal c, and supplies an output signal f to the remaining input terminal of the OR gate 67. When the three input signals are input, the OR gate 67 outputs an output signal g to an output terminal 68. The output signal g is output from the spike noise eliminating circuit 60 as a signal obtained as a result of eliminating spike noise having a predetermined pulse width or smaller from the input signal a, and is input to a digital system or an IIC bus control system.
It should be noted that an IIC bus, which is an abbreviation of an “Inter IC bus”, is a serial bus for use in communications between ICs and in a device. An IIC bus includes two bi-directional control lines for data and a clock.
Next, a description will be given of how the conventional spike noise eliminating circuit 60 can eliminate spike noise, with reference to timing charts shown in FIGS. 11A, 11B, 12A, and 12B.
FIGS. 11A and 11B show the case where the input signal is “0”. FIG. 11A shows the case where spike noise is input. As shown in FIG. 11A, spike noise generated in the input signal a at a time t5 appears in the delay signal b and the delay signal c after a delay of ΔT and 2ΔT by the delay gates 62 and 63, respectively. However, since the output signals d, e, and f of the AND gates 64, 65, and 66, respectively, are all “0”, the output signal g of the OR gate 67 that receives these three signals is also “0”. In this manner, the input signal a has its spike noise eliminated, resulting in the output signal g.
FIG. 11B shows the case where a regular signal is added to the input signal a, so that the signal level is changed from “0” to “1”. As shown in FIG. 11B, when the input signal a is changed to “1” at a time t8, the delay signal b and the delay signal c are changed accordingly after a delay of ΔT and 2ΔT, respectively. The output signal d of the AND gate 64 has its signal level changed to “1” at a time t9 after a delay of ΔT from t8, and the output signals e and f of the AND gates 65 and 66, respectively, have their signal levels changed to “1” at a time t10 after a delay of 2ΔT. Accordingly, the output signal g of the OR gate 67 is changed to “1” at t9 to be maintained as it is. In this manner, the regular input signal a is delayed by ΔT, resulting in the output signal g.
FIGS. 12A and 12B are timing charts, when the input signal a is “1”, showing the case where negative spike noise is eliminated and the case where a regular signal is input so that the signal level is changed from “1” to “0”, respectively. As shown in FIG. 12A, when negative spike noise is added to the input signal a at a time t5, the delay signals b and c from the two delay gates 62 and 63 and the output signals d, e, and f of the three AND gates 64, 65, and 66 are as shown in the figure. The output signal g of the OR gate 67 that receives these three signals is given as a result of eliminating the spike noise. Further, as shown in FIG. 12B, when the input signal a is changed from “1” to “0” at a time t8, the output signal g is changed from “1” to “0” at a time t9 after a delay of a predetermined time ΔT in response to the change in the input signal a.    Patent Document 1: JP 5 (1993)-191226 A